Your qubit is too big for High NA EUV

A size tour of a superconducting quantum chip

In May, imec announced the first qubit device ever made with High-NA EUV lithography: silicon quantum dots with gate gaps of roughly 6 nanometers, patterned with ASML’s newest machine [1].

But is this where all qubit fabrication is heading?

Do you need a roughly 400 million dollar lithography tool [2] to make a qubit?

For superconducting qubits, the answer is no. Not “no, not yet”. Just no.

So let’s do a size tour of a superconducting quantum chip, from the smallest feature to the largest, to see why that is.

The smallest feature on the chip never sees a lithography tool

Start at the very bottom. The heart of every superconducting qubit is the Josephson junction: two aluminum electrodes separated by a tunnel barrier of aluminum oxide, about one to two nanometers thick [3]. That barrier is the smallest and most important feature on the entire chip, and here’s the thing: no lithography tool defines it. You grow it. You let the aluminum surface oxidize in a controlled oxygen atmosphere, and thermodynamics sets the thickness.

I find this worth pausing on. The single most critical dimension in the whole device is set by chemistry, not by optics. No scanner on ASML’s roadmap, at any price, patterns that layer.

The junction electrodes: comfortably 1990s territory

The junction’s lateral dimensions, the part lithography actually defines, are around 100 by 100 nanometers, with typical linear dimensions across designs running from roughly 80 to 680 nanometers [4]. Labs pattern these with electron-beam lithography and shadow evaporation.

Now put that in semiconductor terms. A 100 nm feature corresponds to a logic node the industry passed around 25 years ago. Deep-UV immersion scanners resolve 38 nm half-pitch [2], almost a factor of three below anything on this chip. E-beam persists in academic cleanrooms because it’s flexible and maskless, not because the feature is hard.

And it’s not hypothetical that you can do without e-beam entirely. imec showed in 2024 that you can fabricate complete transmons, junctions included, in a 300 mm CMOS pilot line using nothing but optical lithography and reactive ion etching. No lift-off, no angled evaporation, no e-beam. T1 and T2 above 100 microseconds, with across-wafer statistics [5].

Everything else on the chip is enormous

Climb the ladder from the junction and things get big fast.

The transmon’s shunt capacitor pads: hundreds of micrometers. And this is by design. The physics dictate a large capacitor [6]. Shrink the pads and the electric field concentrates in the lossy surfaces and interfaces. IBM measured this directly years ago: qubits with small footprints are limited by surface loss, qubits with large footprints by other mechanisms.

The readout resonator: a quarter-wave coplanar waveguide at 6 to 7 GHz is around 4 to 5 millimeters of transmission line [6], coiled up like an intestine to fit next to the qubit. Center conductor around 10 micrometers, gaps around 6. These are dimensions you can check with an optical microscope. A good one, but an optical microscope.

A Purcell filter: another millimeter-scale resonator or stub sitting between your readout resonators and the output line, so the qubit doesn’t decay through the very channel you use to measure it [6].

The feedline: centimeters of 50-ohm coplanar waveguide snaking across the chip.

So the full ladder spans from one nanometer (grown, not patterned) through 100 nanometers (the only litho-critical feature) and then jumps three orders of magnitude to the micrometer-to-centimeter scale where the entire rest of the circuit lives.

There is nothing on this chip that an early-2000s stepper can’t resolve. This is also exactly why superconducting qubits don’t scale like transistors: a transmon is thousands of times larger in linear dimension than a transistor gate, and the resonators are larger still.

What superconducting qubits actually need from a fab

If resolution isn’t the bottleneck, what is? Materials and statistics.

The coherence problem is a materials problem: two-level defects in oxides and interfaces, dielectric loss, quasiparticles [6]. The yield problem is a uniformity problem: junction spread maps to qubit frequency spread [4], frequency spread means frequency collisions, and that’s why post-fab tuning techniques (laser annealing, alternating-bias annealing) exist at all.

The scaling problem is an integration problem: flip-chip stacks, through-silicon vias, bump bonds, getting signals in and out of centimeter-scale chips with hundreds of lines.

So, when imec and co run transmons through a CMOS pilot line, the value isn’t the optical lithography tool. It’s the process control, the metrology, the cleanliness, the ability to measure a full wafer and get statistics [5].

Superconducting qubits need the fab discipline of the semiconductor industry.

They just don’t need its latest flagship tool.

References

[1] imec, “World first: imec presents quantum dot qubit device using High NA EUV lithography”, press release, May 2026. imec-int.com

[2] ASML High-NA EUV resolution and pricing: J. van Schoot, “High NA EUV: Getting closer to introduction”, ASML presentation; Tom’s Hardware on EXE pricing and installed base.

[3] Zeng, L. et al., "Atomic structure and oxygen deficiency of the ultrathin aluminium oxide barrier in Al/AlOx/Al Josephson junctions", Scientific Reports 6, 29679 (2016)

[4] Pishchimova, et al., “Improving Josephson junction reproducibility for superconducting quantum circuits: junction area fluctuation”, Scientific Reports 13 (2023).

[5] Van Damme et al., “Advanced CMOS manufacturing of superconducting qubits on 300 mm wafers”, Nature (2024).

[6] Krantz et al., “A quantum engineer’s guide to superconducting qubits”, Applied Physics Reviews 6, 021318 (2019).